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1. general description the 74lvt16245b; 74LVTH16245B is a high-performance bicmos product designed for v cc operation at 3.3 v. this device is a 16-bit transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. the control function implementation minimizes external timing requirements. the device features an output enable input (noe ) for easy cascading and a direction input (ndir) for direction control. 2. features and benefits ? 16-bit bidirectional bus interface ? 3-state buffers ? output capability: +64 ma and ? 32 ma ? ttl input and output switching levels ? input and output interface capab ility to systems at 5 v supply ? bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs ? live insertion and extraction permitted ? power-up 3-state ? no bus current loading when output is tied to 5 v bus ? latch-up protection: ? jesd78b class ii exceeds 500 ma ? esd protection: ? hbm jesd22-a114f exceeds 2000 v ? mm jesd22-a115-a exceeds 200 v 74lvt16245b; 74LVTH16245B 3.3 v 16-bit transceiver; 3-state rev. 07 ? 29 march 2010 product data sheet
74lvt_lvth16245b_7 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserve d. product data sheet rev. 07 ? 29 march 2010 2 of 19 nxp semiconductors 74lvt16245b; 74LVTH16245B 3.3 v 16-bit transceiver; 3-state 3. ordering information 4. functional diagram table 1. ordering information type number package temperature range name description version 74lvt16245bdl ? 40 c to +85 c ssop48 plastic shrink small outline package; 48 leads; body width 7.5 mm sot370-1 74LVTH16245Bdl 74lvt16245bdgg ? 40 c to +85 c tssop48 plastic thin shrink small outline package; 48 leads; body width 6.1 mm sot362-1 74LVTH16245Bdgg 74lvt16245bev ? 40 c to +85 c vfbga56 plastic very thin fine-pitch ball grid array package; 56 balls; body 4.5 7 0.65 mm sot702-1 74lvt16245bbq ? 40 c to +85 c hxqfn60u plastic thermal enhanced extremely thin quad flat package; no leads; 60 terminals; utlp based; body 4 6 0.5 mm sot1134-1 74LVTH16245Bbq pin numbers are shown for ssop48 and tssop48 packages only. fig 1. logic symbol 1dir 1b0 1b1 1b2 1b3 1b4 1b5 1b6 1b7 2b0 2b1 2b2 2b3 2b4 2b5 2b6 2b7 1a0 1a1 1a2 1a3 1a4 1a5 1a6 1a7 2a0 2a1 2a2 2a3 2a4 2a5 2a6 2a7 1oe 2dir 2oe 001aaa78 9
74lvt_lvth16245b_7 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserve d. product data sheet rev. 07 ? 29 march 2010 3 of 19 nxp semiconductors 74lvt16245b; 74LVTH16245B 3.3 v 16-bit transceiver; 3-state pin numbers are shown for ss op48 and tssop48 packages only. fig 2. iec logic symbol g3 g6 3en1 [ ba ] 6en4 [ ba ] 3en2 [ ab ] 6en5 [ ab ] 47 36 46 35 44 33 43 32 41 30 40 29 38 27 37 26 2 13 3 14 5 16 6 17 8 19 9 20 11 22 12 23 1a0 2a1 2a0 2a2 2a3 2a4 2a5 2a6 2a7 2b1 2b2 2b3 2b4 2b5 2b6 2b7 1oe 1dir mna709 1a1 1a2 1a3 1a4 1a5 1a6 1a7 1b0 2b0 1b1 1b2 1b3 1b4 1b5 1b6 1b7 5 4 2 1 25 24 48 1 2oe 2dir
74lvt_lvth16245b_7 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserve d. product data sheet rev. 07 ? 29 march 2010 4 of 19 nxp semiconductors 74lvt16245b; 74LVTH16245B 3.3 v 16-bit transceiver; 3-state 5. pinning information 5.1 pinning fig 3. pin configuration for ssop48 and tsso p48 fig 4. pin configuration for vfbga56 74lvt16245b 74LVTH16245B 1dir 1oe 1b0 1a0 1b1 1a1 gnd gnd 1b2 1a2 1b3 1a3 v cc v cc 1b4 1a4 1b5 1a5 gnd gnd 1b6 1a6 1b7 1a7 2b0 2a0 2b1 2a1 gnd gnd 2b2 2a2 2b3 2a3 v cc v cc 2b4 2a4 2b5 2a5 gnd gnd 2b6 2a6 2b7 2a7 2dir 2oe 001aae471 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 001aae47 4 1dir n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. 1b1 1b3 1b5 1b7 2b0 2b2 2b4 2b6 2dir a b c d e f g h j k 1b0 1b2 1b4 1b6 2b1 2b3 2b5 2b7 gnd v cc gnd gnd v cc gnd gnd v cc gnd gnd v cc gnd 1a0 1a2 1a4 1a6 2a1 2a3 2a5 2a7 1oe 1a1 1a3 1a5 1a7 2a0 2a2 2a4 2a6 1 transparent top view 234 74lvt16245b 56 2oe
74lvt_lvth16245b_7 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserve d. product data sheet rev. 07 ? 29 march 2010 5 of 19 nxp semiconductors 74lvt16245b; 74LVTH16245B 3.3 v 16-bit transceiver; 3-state (1) the die substrate is attached to this pad using conductive die attach material. it can not be used as a supply pin or input. fig 5. pin configuration sot1134-1 (hxqfn60u) d1 d3 a16 a15 a14 a13 a12 a11 d2 b9 gnd (1) b10 d7 a17 a18 b11 a19 b12 a20 b13 a21 b14 b8 a10 d6 a9 a8 b7 b6 a7 b5 a6 a22 b15 a23 b16 a24 b17 a25 a26 d8 d4 a27 b18 a28 a29 b19 b20 a30 a31 a32 b4 a5 b3 b2 b1 d5 a4 a3 a2 a1 74lvt16245b 74LVTH16245B 001aaj65 6 transparent top view terminal 1 index area
74lvt_lvth16245b_7 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserve d. product data sheet rev. 07 ? 29 march 2010 6 of 19 nxp semiconductors 74lvt16245b; 74LVTH16245B 3.3 v 16-bit transceiver; 3-state 5.2 pin description 6. functional description 6.1 function table [1] h = high voltage level; l = low voltage level; x = don?t care; z = high-impedance off-state. table 2. pin description symbol pin description sot370-1 and sot362-1 sot702-1 sot1134-1 1dir, 2dir 1, 24 a1, k1 a30, a13 direction control input 1b0 to 1b7 2, 3, 5, 6, 8, 9, 11, 12 b2, b1, c2, c1, d2, d1, e2, e1 b20, a31, d5, d1, a2, b2, b3, a5 data input/output 2b0 to 2b7 13, 14, 16, 17, 19, 20, 22, 23 f1, f2, g1, g2, h1, h2, j1, j2 a6, b5, b6, a9, d2, d6, a12, b8 data input/output gnd 4, 10, 15, 21, 28, 34, 39, 45 b3, d3, g3, j3, j4, g4, d4, b4 a32, a3, a8, a11, a16, a19, a24, a27 ground (0 v) v cc 7, 18, 31, 42 c3, h3, h4, c4 a1, a10, a17, a26 supply voltage 1oe , 2oe 48, 25 a6, k6 a29, a14 output enable input (active low) 2a0 to 2a7 36, 35, 33, 32, 30, 29, 27, 26 f6, f5, g6, g5, h6, h5, j6, j5 a21, b13, b12, a18, d3, d7, a15, b10 data input/output 1a0 to 1a7 47, 46, 44, 43, 41, 40, 38, 37 b5, b6, c5, c6, d5, d6, e5, e6 b18, a28, d8, d4, a25, b16, b15, a22 data input/output n.c. - a2, a3, a4, a5, k2, k3, k4, k5 a4, a7, a20, a23, b1, b4, b7, b9, b11, b14, b17, b19 not connected table 3. function table [1] control input/output noe ndir nan nbn l l output nan = nbn input l h input output nbn = nan hxz z
74lvt_lvth16245b_7 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserve d. product data sheet rev. 07 ? 29 march 2010 7 of 19 nxp semiconductors 74lvt16245b; 74LVTH16245B 3.3 v 16-bit transceiver; 3-state 7. limiting values [1] the input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. [2] the performance capability of a high-perfo rmance integrated circuit in conjunction with its thermal environment can create j unction temperatures which are detrimental to reliability. [3] above 60 c the value of p tot derates linearly with 5.5 mw/k. [4] above 70 c the value of p tot derates linearly with 1.8 mw/k. 8. recommended operating conditions table 4. limiting values in accordance with the absolute maximum rating system (iec 60134). voltages are referenced to gnd (ground = 0 v). symbol parameter conditions min max unit v cc supply voltage ? 0.5 +4.6 v v i input voltage [1] ? 0.5 +7.0 v v o output voltage output in off-state or high-state [1] ? 0.5 +7.0 v i ik input clamping current v i < 0 v ? 50 - ma i ok output clamping current v o < 0 v ? 50 - ma i o output current output in low-state - 128 ma output in high-state ? 64 - ma t stg storage temperature ? 65 +150 c t j junction temperature [2] - 150 c p tot total power dissipation t amb = ? 40 c to +85 c; (t)ssop48 package [3] - 500 mw vfbga56 package [4] - 1000 mw hxqfn60u package [4] - 1000 mw table 5. recommended operating conditions symbol parameter conditions min typ max unit v cc supply voltage 2.7 - 3.6 v v i input voltage 0 - 5.5 v v ih high-level input voltage 2.0 - - v v il low-level input voltage - - 0.8 v i oh high-level output current ? 32 - - ma i ol low-level output current none - - 32 ma current duty cycle 50 %; f i 1khz --64ma t amb ambient temperature in free-air ? 40 - +85 c t/ v input transition rise and fall rate outputs enabled - - 10 ns/v
74lvt_lvth16245b_7 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserve d. product data sheet rev. 07 ? 29 march 2010 8 of 19 nxp semiconductors 74lvt16245b; 74LVTH16245B 3.3 v 16-bit transceiver; 3-state 9. static characteristics table 6. static characteristics at recommended operating conditions; volt ages are referenced to gnd (ground = 0 v). symbol parameter conditions min typ max unit t amb = ? 40 c to +85 c [1] v ik input clamping voltage v cc = 2.7 v; i ik = ? 18 ma ? 1.2 ? 0.85 - v v oh high-level output voltage i oh = ? 100 a; v cc = 2.7 v to 3.6 v v cc ? 0.2 v cc -v i oh = ? 8ma; v cc = 2.7 v 2.4 2.5 - v i oh = ? 32 ma; v cc = 3.0 v 2.0 2.3 - v v ol low-level output voltage v cc = 2.7 v i ol = 100 a - 0.07 0.2 v i ol = 24 ma - 0.3 0.5 v v cc = 3.0 v i ol = 16 ma - 0.25 0.4 v i ol = 32 ma - 0.3 0.5 v i ol = 64 ma - 0.4 0.55 v i i input leakage current control pins v cc = 3.6 v; v i = v cc or gnd - 0.1 1 a v cc = 0 v or 3.6 v; v i = 5.5 v - 0.1 10 a input/output data pins; v cc = 3.6 v [2] v i = 5.5 v - 0.1 20 a v i = v cc -0.510 a v i = 0 v ? 5 ? 0.1 - a i off power-off leakage current v cc = 0 v; v i or v o = 0v to4.5v - 0.1 100 a i bhl bus hold low current v cc = 3 v; v i = 0.8 v [3] 75 135 - a i bhh bus hold high current v cc = 3 v; v i = 2.0 v - ? 135 ? 75 a i bhlo bus hold low overdrive current nan input; v i =0vto3.6v;v cc =3.6v 500 - - a i bhho bus hold high overdrive current nan input; v i =0vto3.6v;v cc =3.6v - - ? 500 a i lo output leakage current outpu t in high-state when v o >v cc ; v o = 5.5 v; v cc =3.0v - 75 125 a i o(pu/pd) power-up/power-down output current v cc 1.2 v; v o = 0.5 v to v cc ; v i = gnd or v cc ; noe = don?t care [4] -40 100 a i cc supply current v cc = 3.6 v; v i = gnd or v cc ; i o =0a outputs high - 0.07 0.12 ma outputs low - 4.7 6.0 ma outputs disabled [5] - 0.07 0.12 ma i cc additional supply current per input pin; v cc = 3.0 v to 3.6 v; one input at v cc ? 0.6 v, other inputs at v cc or gnd [6] -0.10.2ma c i input capacitance pins ndir and noe , v o = 0v or 3.0v - 3 - pf
74lvt_lvth16245b_7 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserve d. product data sheet rev. 07 ? 29 march 2010 9 of 19 nxp semiconductors 74lvt16245b; 74LVTH16245B 3.3 v 16-bit transceiver; 3-state [1] typical values are measured at v cc = 3.3 v and at t amb = 25 c. [2] unused pins at v cc or gnd. [3] this is the bus hold overdrive current require d to force the input to the opposite logic state. [4] this parameter is valid for any v cc between 0 v and 1.2 v with a transition time of up to 10 ms. from v cc = 1.2 v to v cc = 3.3 v 0.3 v a transition time of 100 s is permitted. this parameter is valid for t amb = 25 c only. [5] i cc is measured with outputs pulled to v cc or gnd. [6] this is the increase in supply current for each input at the specified voltage level other than v cc or gnd. 10. dynamic characteristics [1] all typical values are at v cc = 3.3 v and t amb = 25 c. c io(off) off-state input/output capacitance pins nan and nbn, outputs disabled; v o = gnd or v cc -9-pf table 6. static characteristics ?continued at recommended operating conditions; volt ages are referenced to gnd (ground = 0 v). symbol parameter conditions min typ max unit table 7. dynamic characteristics voltages are referenced to gnd (ground = 0 v); for test circuit see figure 8 . symbol parameter conditions min typ [1] max unit t amb = ? 40 c to +85 c t plh low to high propagation delay nan to nbn or nbn to nan; see figure 6 v cc = 2.7 v - - 3.5 ns v cc = 3.0 v to 3.6 v 1.0 1.9 3.3 ns t phl high to low propagation delay nan to nbn or nbn to nan; see figure 6 v cc = 2.7 v - - 3.5 ns v cc = 3.0 v to 3.6 v 1.0 1.7 3.3 ns t pzh off-state to high propagation delay noe to nan or nbn; see figure 7 v cc = 2.7 v - - 5.3 ns v cc = 3.0 v to 3.6 v 1.0 2.8 4.5 ns t pzl off-state to low propagation delay noe to nan or nbn; see figure 7 v cc = 2.7 v - - 5.1 ns v cc = 3.0 v to 3.6 v 1.0 2.8 4.1 ns t phz high to off-state propagation delay noe to nan or nbn; see figure 7 v cc = 2.7 v - - 5.7 ns v cc = 3.0 v to 3.6 v 1.5 3.2 5.1 ns t plz low to off-state propagation delay noe to nan or nbn; see figure 7 v cc = 2.7 v - - 4.6 ns v cc = 3.0 v to 3.6 v 1.5 3.0 4.6 ns
74lvt_lvth16245b_7 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserve d. product data sheet rev. 07 ? 29 march 2010 10 of 19 nxp semiconductors 74lvt16245b; 74LVTH16245B 3.3 v 16-bit transceiver; 3-state 11. waveforms measurements points are given in table 8 . v ol and v oh are typical voltage output levels that occur with the output load. fig 6. propagation delay input (nan, nbn) to output (nbn, nan) mna4 77 nan, nbn input nbn, nan output t phl t plh gnd v i v m v m v oh v ol measurements points are given in table 8 . v ol and v oh are typical voltage output levels that occur with the output load. fig 7. 3-state output enable and disable times 001aaj65 8 t pzl nan or nbn output nbn or nan output noe input v ol v oh 3.0 v v i v m 0 v 0 v t plz t pzh t phz v x v y v m v m table 8. measurement points input output v m v m v x v y 1.5 v 1.5 v v ol + 0.3 v v oh ? 0.3 v
74lvt_lvth16245b_7 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserve d. product data sheet rev. 07 ? 29 march 2010 11 of 19 nxp semiconductors 74lvt16245b; 74LVTH16245B 3.3 v 16-bit transceiver; 3-state test data is given in table 9 . definitions test circuit: r l = load resistance. c l = load capacitance including jig and probe capacitance. r t = termination resistance should be equal to output impedance z o of the pulse generator. v ext = external voltage for measuring switching times. fig 8. test circuit for measuring switching times v ext v cc v i v o 001aae2 35 dut c l r t r l r l pulse generator v m v m t w t w 10 % 90 % 0 v v i v i negative pulse positive pulse 0 v v m v m 90 % 10 % t f t r t r t f table 9. test data input load v ext v i f i t w t r , t f c l r l t phz , t pzh t plz , t pzl t plh , t phl 2.7 v 10 mhz 500 ns 2.5 ns 50 pf 500 gnd 6 v open
74lvt_lvth16245b_7 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserve d. product data sheet rev. 07 ? 29 march 2010 12 of 19 nxp semiconductors 74lvt16245b; 74LVTH16245B 3.3 v 16-bit transceiver; 3-state 12. package outline fig 9. package outline sot370-1 (ssop48) unit a 1 a 2 a 3 b p cd (1) e (1) eh e ll p qz y w v references outline version european projection issue date iec jedec jeita mm 0.4 0.2 2.35 2.20 0.25 0.3 0.2 0.22 0.13 16.00 15.75 7.6 7.4 0.635 1.4 0.25 10.4 10.1 1.0 0.6 1.2 1.0 0.85 0.40 8 0 o o 0.18 0.1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. sot370-1 99-12-27 03-02-19 (1) w m b p d h e e z e c v m a x a y 48 25 mo-118 24 1 a a 1 a 2 l p q detail x l (a ) 3 pin 1 index 0 5 10 mm scale ssop48: plastic shrink small outline package; 48 leads; body width 7.5 mm sot370 -1 a max. 2.8
74lvt_lvth16245b_7 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserve d. product data sheet rev. 07 ? 29 march 2010 13 of 19 nxp semiconductors 74lvt16245b; 74LVTH16245B 3.3 v 16-bit transceiver; 3-state fig 10. package outline sot362-1 (tssop48) unit a 1 a 2 a 3 b p cd (1) e (2) eh e ll p qz y w v references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.2 0.1 8 0 o o 0.1 dimensions (mm are the original dimensions). notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. sot362-1 99-12-27 03-02-19 w m a a 1 a 2 d l p q detail x e z e c l x (a ) 3 0.25 124 48 25 y pin 1 index b h 1.05 0.85 0.28 0.17 0.2 0.1 12.6 12.4 6.2 6.0 0.5 1 0.25 8.3 7.9 0.50 0.35 0.8 0.4 0.08 0.8 0.4 p e v m a a tssop48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm sot362 -1 a max. 1.2 0 2.5 5 mm scale mo-153
74lvt_lvth16245b_7 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserve d. product data sheet rev. 07 ? 29 march 2010 14 of 19 nxp semiconductors 74lvt16245b; 74LVTH16245B 3.3 v 16-bit transceiver; 3-state fig 11. package outline sot702-1 (vfbga56) 0.65 a 1 b a 2 unit d y e references outline version european projection issue date 02-08-08 03-07-01 iec jedec jeita mm 1 0.3 0.2 0.7 0.6 4.6 4.4 y 1 7.1 6.9 0.45 0.35 0.08 0.1 e 1 3.25 e 2 5.85 dimensions (mm are the original dimensions) sot702-1 mo-225 e 0.15 v 0.08 w 0 2.5 5 mm scale sot702 -1 v fbga56: plastic very thin fine-pitch ball grid array package; 56 balls; body 4.5 x 7 x 0.65 mm a max. a a 2 a 1 detail x y y 1 c e e b x d e c a b c d e f h g j k 246 135 ball a1 index area b a e 2 e 1 1/2 e 1/2 e a c c b ? v m ? w m ball a1 index area
74lvt_lvth16245b_7 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserve d. product data sheet rev. 07 ? 29 march 2010 15 of 19 nxp semiconductors 74lvt16245b; 74LVTH16245B 3.3 v 16-bit transceiver; 3-state fig 12. package outline sot1134-1 (hxqfn60u) references outline version european projection issue date iec jedec jeita sot1134-1 - - - - - - - - - sot1134-1_po 08-12-17 09-01-22 unit mm max nom min 0.50 0.48 0.46 0.05 0.02 0.00 4.1 4.0 3.9 1.90 1.85 1.80 6.1 6.0 5.9 3.90 3.85 3.80 1 2.5 4.5 0.125 0.075 0.025 0.07 a dimensions h xqfn60u: plastic thermal enhanced extremely thin quad flat package; no leads; 6 0 terminals; utlp based; body 4 x 6 x 0.5 mm sot1134 -1 a 1 b 0.35 0.30 0.25 dd h ee h 0.08 0.1 yy 1 e 0.5 e 1 e 2 e 3 3 e 4 er 0.5 k 0.25 0.20 0.15 l 0.35 0.30 0.25 l 1 v 0.05 w 0 2.5 5 mm scale a c b v c w b a terminal 1 index area d e c y c y 1 x detail x a a 1 e r e 3 e 4 e 2 e 1 e e 1/2 e 1/2 e b a c b v c w k l b20 b18 a27 d8 d4 a32 d5 d7 d6 d1 d3 d2 d h e h l 1 terminal 1 index area a11 a16 b10 b8 a17 b11 b17 a26 a1 b1 a10 b7
74lvt_lvth16245b_7 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserve d. product data sheet rev. 07 ? 29 march 2010 16 of 19 nxp semiconductors 74lvt16245b; 74LVTH16245B 3.3 v 16-bit transceiver; 3-state 13. abbreviations 14. revision history table 10. abbreviations acronym description bicmos bipolar complementary metal oxide semiconductor dut device under test esd electrostatic discharge hbm human body model mm machine model ttl transistor-transistor logic table 11. revision history document id release date data sheet status change notice supersedes 74lvt_lvth16245b_7 20100329 product data sheet - 74lvt_lvth16245b_6 modifications: ? 74lvt16245bbq and 74LVTH16245Bbq changed from huqfn60u (sot1025-1) to hxqfn60u (sot1134-1) package. 74lvt_lvth16245b_6 20090409 product data sheet - 74lvt_lvth16245b_5 modifications: ? section 2 : class ii added for latch-up protection. ? table 6 : conditions for bus hold overdrive current have changed. 74lvt_lvth16245b_5 20090312 product data sheet - 74lvt_lvth16245b_4 74lvt_lvth16245b_4 20060323 product data sheet - 74lvt16245b_3 74lvt16245b_3 20021031 product data sheet - 74lvt16245b_2 74lvt16245b_2 19980219 product specification - 74lvt16245b_1 74lvt16245b_1 19940523 produ ct specification - -
74lvt_lvth16245b_7 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserve d. product data sheet rev. 07 ? 29 march 2010 17 of 19 nxp semiconductors 74lvt16245b; 74LVTH16245B 3.3 v 16-bit transceiver; 3-state 15. legal information 15.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 15.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 15.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interrupt ion, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use in automotive applications ? this nxp semiconductors product has been qua lified for use in automotive applications. the product is not desi gned, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be ex pected to result in personal injury, death or severe property or environmental dam age. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on a weakness or default in the customer application/use or the application/use of customer?s third party customer(s) (hereinafter both referred to as ?application?). it is customer?s sole responsibility to check whether the nxp semiconductors product is suitable and fit for the application planned. customer has to do all necessary testing for the application in order to avoid a default of the application and the product. nxp semiconducto rs does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. 15.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this docu ment contains the product specification.
74lvt_lvth16245b_7 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserve d. product data sheet rev. 07 ? 29 march 2010 18 of 19 nxp semiconductors 74lvt16245b; 74LVTH16245B 3.3 v 16-bit transceiver; 3-state 16. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
nxp semiconductors 74lvt16245b; 74LVTH16245B 3.3 v 16-bit transceiver; 3-state ? nxp b.v. 2010. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 29 march 2010 document identifier: 74lvt_lvth16245b_7 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 17. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 functional description . . . . . . . . . . . . . . . . . . . 6 6.1 function table . . . . . . . . . . . . . . . . . . . . . . . . . . 6 7 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7 8 recommended operating conditions. . . . . . . . 7 9 static characteristics. . . . . . . . . . . . . . . . . . . . . 8 10 dynamic characteristics . . . . . . . . . . . . . . . . . . 9 11 waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 12 package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 13 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16 14 revision history . . . . . . . . . . . . . . . . . . . . . . . . 16 15 legal information. . . . . . . . . . . . . . . . . . . . . . . 17 15.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 17 15.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 15.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 15.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17 16 contact information. . . . . . . . . . . . . . . . . . . . . 18 17 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

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